The present invention relates to a semiconductor structure comprising a silicon-containing substrate having a peripheral edge surface and a circuit structure circumscribed by a crackstop structure. Through-silicon conductive vias are configured to connect the circuit structure to the peripheral edge surface without penetrating the crackstop structure.
Three-dimensional (3D) stacking of integrated circuits have improved circuit performance. More specifically, advancements in the area of semiconductor fabrication have enabled the manufacturing of integrated circuits that have a high density of electronic components.
Fabrication of 3D integrated circuits includes at least two silicon die stacked vertically. Vertically stacked die can reduce interconnect wiring length and increase semiconductor device density. Deep through-substrate/through-silicon vias (TSVs) may be formed to provide interconnections and electrical connectivity between the electronic components of the 3D integrated circuits. Such TSVs may have high aspect ratios, where the via height is large with respect to the via width, to save valuable area in an integrated circuit design. Therefore, semiconductor device density can be increased and total length of interconnect wiring may be decreased by incorporating TSVs in 3D integrated circuits.